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25AA160/25LC160/25C160
FIGURE 3-7:
CS
WRITE STATUS REGISTER TIMING SEQUENCE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
instruction
data to Status register
SI
0
0
0
0
0
0
0
1
7
6
5
4
3
2
1
0
High-impedance
SO
3.7
Data Protection
3.8
Power On State
The following protection has been implemented to
The 25XX160 powers on in the following state:
prevent inadvertent writes to the array:
? The write enable latch is reset on power-up
? A WRITE ENABLE instruction must be issued to
set the write enable latch
? After a byte write, page write, or Status register
write, the write enable latch is reset
? CS must be set high after the proper number of
clock cycles to start an internal write cycle
? Access to the array during an internal write cycle
is ignored and programming is continued
?
?
?
?
The device is in low power Standby mode (CS = 1 )
The write enable latch is reset
SO is in high-impedance state
A low level on CS is required to enter active state
TABLE 3-3:
WRITE-PROTECT FUNCTIONALITY MATRIX
WPEN
X
0
1
X
WP
X
X
Low
High
WEL
0
1
1
1
Protected Blocks
Protected
Protected
Protected
Protected
Unprotected Blocks
Protected
Writable
Writable
Writable
Status Register
Protected
Writable
Protected
Writable
? 2004 Microchip Technology Inc.
DS21231D-page 11
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